This invention relates to a modification of a phase and frequency detector (PFD) in order to correct an undesirable preconditioned state resulting from a missing input clock source.
Phase Locked Loop (PLL) implementations typically employ some variation of a phase and frequency detector (PFD) circuit to facilitate the adjustments needed to lock the system output clock to an input reference clock. A standard PFD that is commonly used because of its simplicity and accuracy is shown in FIG. 1 and is indicated by the general reference character 100. The intent is to allow the PLL to operate smoothly and with minimal phase disturbances, even when there are missing pulses on the input reference clock signal. This occurrence is common in modem communications networks where more than one input reference signal may be used and where each may correspond to different switches and routers operating under unique clock regimes. As packets, for example, are passed from one router to the next, the synchronizing clock information of the first router may also be passed to the second router for data or flow control purposes. Alternatively, one clock source may fail and there may be a system integrity requirement to switchover to another input reference source.
The PFD utilized as part of the overall PLL design must be equipped to efficiently handle the missing input source scenario. It is also desirable for the circuit to operate so that its resulting phase capture range is minimized. If the range is too large, it will take much longer for the PLL to lock on to the input reference clock. This can be the case for even only a single missing input reference clock pulse.
Once again referring to FIG. 1, the basic operation of the system 100 is well known and understood in the art. The essential features of this approach during normal operation will now be described.
The circuit 100 includes D-type flip-flop registers 102 and 104. The first register 102 receives the first input source, INPUT A, as its clk-input. The D-input of register 102 is connected to the positive supply voltage, VDD. The Q-output of register 102 connects to first phase indicator signal 110, UP. The second register 104 receives the second input source, INPUT B, as its clk-input. The D-input of register 104 is connected to the positive supply voltage, VDD. The Q-output of register 104 connects to the second phase indicator signal 112, DOWN. The two phase indicator signals, UP and DOWN, are also inputs to NAND-gate 106. The output of the NAND-gate is the active-low reset control signal 108, RESETB, and this connects to the reset-inputs of registers 102 and 104. There may also be additional delay along with the NAND-gate operation to assure sufficient RESETB pulse width.
FIG. 2 shows a timing diagram corresponding to the normal operation of the PFD of FIG. 1, and these figures should be viewed together. The INPUT A waveform 202 is shown with a phase difference relative to the INPUT B waveform 204. The UP phase indicator waveform 206 goes high upon detection of the INPUT A rising edge. This is the D-type flip-flop operation when the D-input is connected to a logic high state. Similarly, the DOWN phase indicator waveform 208 goes high upon detection of the INPUT B rising edge. Because of the NAND-gate 106 function, the reset control signal waveform 210 goes low and this causes registers 102 and 104 to discharge (i.e., reset) phase indicator signals UP and DOWN, respectively.
A problem with the PFD of FIG. 1 is that the normal phase capture range is essentially +/xe2x88x92360 degrees. For the case of a missing input reference clock pulse (i.e., input source), or any number of pulses, this circuit gets into a preconditioned state near xe2x88x92360 degrees. The ramification for the PLL is that it will attempt to move its phase lock position by nearly an entire clock cycle in order to match the input reference clock. This is an undesirable situation because it will cause the PLL to take more time to lock by using an inefficient path and it can also lead to unnecessary phase disturbances.
The undesirable preconditioned state will now be described with reference to both FIG. 1 and FIG. 3.
In FIG. 3, the INPUT A waveform 302 is shown along with the INPUT B waveform 304. In this scenario, the INPUT A waveform has the same relative position as illustrated in FIG. 2, but after some previous missing pulse high (i.e., missing clock pulse). The first phase indicator signal, UP, waveform 306 goes high upon the rising edge of INPUT A, as also in the example case of FIG. 2. However, the second phase indicator signal, DOWN, waveform 308 remains stuck high prior to the INPUT B rising edge. This is due to a missing reset control pulse resulting from the missing INPUT A pulse. Without the INPUT A rising edge to activate the first phase indicator signal, UP, that input to the NAND-gate 106 of FIG. 1 remains low. This forces the reset control signal 108 to remain in its inactive high state. Thus, the second phase indicator signal, DOWN, remains high for a longer duration because it is not reset by the reset control signal, indicated by its associated waveform 310, activating until the following rising edge of INPUT A. As shown in FIG. 3, the circuit remains in this preconditioned state of inverted DOWN signal operation due to the improper resetting of the registers.
It would be desirable to arrive at some way of providing phase and frequency detection and control that would allow for missing input clock pulses with minimal phase disturbances and high PLL locking efficiency by ensuring that the PFD does not enter the undesirable preconditioned state.
A phase and frequency detector (PFD) utilizes three registers and a control circuit. The first register receives a first input source and a first reset control signal and it outputs a first phase indicator signal. The second register receives a second input source and a second reset control signal and it outputs a second phase indicator signal. The third register receives an enable control signal and a synchronizing signal, which may be an inverted version of the second input source, and it outputs a second reset control signal. The control circuit receives the first phase indicator signal, the second phase indicator signal, and the second reset control signal and outputs the first reset control signal.
A reset operation on all registers occurs when a missing input reference source pulse has been detected. This causes the enable control signal to go high and activates the second reset control signal. This second reset control signal then activates the first reset control signal, regardless of the states of the first and the second phase indicator signals. The PFD then returns to normal operation upon the activation of the first reset control signal.
An advantage of this invention is that the phase disturbance due to missing input reference source pulses on the clock output of the PLL system that utilizes this PFD is minimized.
Another advantage of this invention is that the same circuitry can be used for either phase and frequency detection or only phase detection.
Another advantage of this invention is that the capture range can be limited to +/xe2x88x92180 degrees instead of +/xe2x88x92360 degrees based on a single enable control signal.
Yet another advantage of this invention is that it allows for both frequency locking and nearest edge locking approaches.